A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3x3 kernel. The proof-of-concept circuit is implemented in 0.35 µm CMOS technology, and contains a 64x64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 µW per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.
Authors
Additional information
- DOI
- Digital Object Identifier link open in new tab 10.1109/tcsi.2012.2215803
- Category
- Publikacja w czasopiśmie
- Type
- artykuł w czasopiśmie wyróżnionym w JCR
- Language
- angielski
- Publication year
- 2013
