The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA–based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.
Authors
- Grzegorz Mrugalski,
- Nilanjan Mukherejee,
- Artur Pogiel,
- Janusz Rajski,
- dr inż. Maciej Trawka,
- Jerzy Tyszer
Additional information
- DOI
- Digital Object Identifier link open in new tab 10.1109/ats.2014.25
- Category
- Aktywność konferencyjna
- Type
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Language
- angielski
- Publication year
- 2014
