Repozytorium publikacji - Politechnika Gdańska

In this paper an analog voltage-mode median filter, which operates on a 3 × 3 kernel is presented. The filter is implemented in a 0.35 μm CMOS technology. The proposed solution is based on voltage comparators and a bubble sort configuration. As a result, a fast (34 ns) time response with low power consumption (1.25 mW for 3.3 V) is achieved. The key advantage of the configuration is relatively high accuracy of signal processing, which allows the calculation of the median of signals with the difference in amplitude as small as 10 mV. This feature allows the application of the filter to vision systems with up to 7 bit equivalent resolution. The analytical and statistical analysis of the filter resolution, and analysis of its speed limitations are presented and compared to measurement results. Based on the achieved results, a set of guidelines for the filter design and optimisation is presented.

Autorzy

• dr hab. inż. Waldemar Jendernalik link otwiera się w nowej karcie ,
• dr hab. inż. Grzegorz Blakiewicz link otwiera się w nowej karcie ,
• dr hab. inż. Jacek Jakusz link otwiera się w nowej karcie ,
• prof. dr hab. inż. Stanisław Szczepański link otwiera się w nowej karcie