Repozytorium publikacji - Politechnika Gdańska

The paper presents application called FIReWORK, that allows for automatic creation of the VHDL hardware structures of FIR filters. Automat- ically generated specialized hardware solutions dedicated to the FPGA and ASIC are commonly known as Intellectual Property Cores. The essential fu- ture of the application is easy initialization of FIR filter parameters in GUI, and then automatically design, calculate and generate the IP Core struc- ture of the filter. The hardware realization is based on the Residue Number System, as a main arithmetic. Current structure of the application, the main objectives of the project, design assumptions and benefits are discussed. Keywords: FIR filtering, FPGA, hardware generation, IP Core, software generator, VHDL

Autorzy

• dr inż. Robert Smyk link otwiera się w nowej karcie