Repozytorium publikacji - Politechnika Gdańska

The work covers several issues of realization of digital structures for pipelined processing of real and complex signals with the use of binary arithmetic and residue arithmetic. Basic rules of performing operations in residue arithmetic are presented along with selected residue number systems for processing of complex signals and computation of convolution. Subsequently, methods of conversion of numbers from weighted systems to the residue number system are shown. Three pipelined structures of two-operand modular adders based on known algorithms are described as well as a new pipelined two-operand modular adder. Architectures of B/RNS converters are demonstrated that use unified channels or periodicity. Methods of RNS/B conversion and respective converter architectures are described. A new five-bit residue multiplier is proposed and compared with other known solutions. New methods of scaling and pipelined division are reported. Finally necessary relationships are given that are needed to design a pipelined residue divider and a radix-4 MQRNS FFT processor. The work concludes with a description of developed exemplary FPGA implementations of TCS/RNS and RNS/B converters, residue scaler, divider, FIR filter and a radix-4 MQRNS FFT butterfly. Finally an experimental verification is performed of the pipelined MQRNS FFT processor by comparison of spectra of transformer inrush and short-circuit currents obtained using this processor and a floating-point FFT algorithm.

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