In this paper hardware and software realization of direct and inverse AES cryptographic algorithm is presented. Both implementations were made using the Virtex-II FPGA and were practically tested. As the criteria of comparison, the resource utilization, achieved performance and power dissipation were chosen. Hardware realization increases throughput of conversion about 190 times over software implementation and decreases the energy required to process one data packet about 80 times, while resource utilization is about five times greater.
Autorzy
Informacje dodatkowe
- Kategoria
- Publikacja w czasopiśmie
- Typ
- artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
- Język
- angielski
- Rok wydania
- 2007
