The paper presents the hardware implementation of the improved alpha max plus beta min algorithm for calculating the magnitude of complex numbers. This version of the algorithm requires the general division which is performed using a noniterative multiplicative division algorithm. We analyze in detail the division algorithm, its error and the impact of finite word-length signal representations on the assumed total computation error. An analysis is performed to determine the binary length of operands at each stage of the magnitude calculator in order not to exceed the assumed total error. An FPGA implementation is presented along with its hardware requirement and delay.
Autorzy
Informacje dodatkowe
- Kategoria
- Publikacja w czasopiśmie
- Typ
- artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
- Język
- angielski
- Rok wydania
- 2016
