Repozytorium publikacji - Politechnika Gdańska

An experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller by 30% than that for the VHDL designed converter.

Autorzy

• dr inż. Robert Smyk link otwiera się w nowej karcie ,
• dr hab. inż. Maciej Czyżak link otwiera się w nowej karcie