Repozytorium publikacji - Politechnika Gdańska

This paper presents verification and benchmarking required for the development of a coprocessor digital circuit for integer multiple-precision arithmetic (MPA). Its code is developed, with the use of very high speed integrated circuit hardware description language (VHDL), as an intellectual property core. Therefore, it can be used by a final user within their own computing system based on field-programmable gate arrays (FPGAs). The coprocessor is still under development and its open-source code is available on the Internet, based on the Mozilla Public License. Therefore, verification and benchmarking of the coprocessor code are vitally important issues as the sources are continually downloaded by users all over the world. In this contribution, we present software tools developed as a part of the system, allowing for detection of errors in the coprocessor code as well as for execution of its benchmarking tests. The research conclusion is that, without well-designed verification and benchmarking software tools, the development of any advanced digital circuit, such as a coprocessor, is actually impossible in realistic time. It stems from the fact that 60% of the project repository include hardware-description codes, whereas the rest of the codes support correct development of the project, i.e., verification and benchmarking in the design process.

Autorzy

• dr hab. inż. Tomasz Stefański link otwiera się w nowej karcie ,
• dr Kamil Rudnicki,
• dr inż. Wojciech Żebrowski