Multilevel inverter topologies provide several advantages over two-level inverter configuration. These benefits are the reason for the growing interest in multilevel topologies among research society. One of the most popular topological concepts (diode and active switch clamping) requires neutral-point potential balancing due to series-connected capacitor banks across the input dc link in such derived inverter configurations. This paper presents a Sinusoidal PWM (SPWM) scheme that ensures balanced and reduced input capacitor voltages' variations in single-phase T-type inverter. Comparison analyses with existing carrier-based pulse-width modulation methods are provided. Simulation results are provided which showcase the effectiveness of the control approach. Experimental validation of these results was provided with a five-level single-phase T-type VSI; that supplies single-phase RL load.
Autorzy
Informacje dodatkowe
- Kategoria
- Aktywność konferencyjna
- Typ
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Język
- angielski
- Rok wydania
- 2022
