A simple model is derived and verified for evaluating the effect of parasitic capacitances on the dead-time related voltage distortion in multilevel NPC voltage source inverters. The model permits well-defined and precise compensation of dead-time distortion, exhibiting meaningful improvement on compensation methods neglecting the effects of parasitic capacitances. A simple formula is given for evaluating the capacitances as serial/parallel connections of transistor capacitances and external capacitances (introduced by the cables and load).
Authors
Additional information
- DOI
- Digital Object Identifier link open in new tab 10.1109/isie.2011.5984442
- Category
- Aktywność konferencyjna
- Type
- materiały konferencyjne indeksowane w Web of Science
- Language
- angielski
- Publication year
- 2011
