This paper presents the adaptation of a 3D integration concept previously used with vertical devices to lateral GaN devices. This 3D integration allows to reduce loop inductance, to ensure more symmetrical design with especially limited Common Mode emission, thanks to a low middle point stray capacitance. This reduction has been achieved by both working on the power layout and including a specific shield between the devices and the heatsink. The performances of this 3D layout have been verified in comparison with a more conventional 2D implementation, using both simulations and measurements.
Authors
- Paweł Derkacz link open in new tab ,
- prof. dr hab. inż. Piotr Chrzan link open in new tab ,
- dr Pierre-Olivier Jeannin,
- dr hab. inż. Piotr Musznicki link open in new tab ,
- dr Mickael Petit,
- prof Jean-Luc Schanen
Additional information
- Category
- Aktywność konferencyjna
- Type
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Language
- angielski
- Publication year
- 2020
