Repozytorium publikacji - Politechnika Gdańska

This paper presents the adaptation of a 3D integration concept previously used with vertical devices to lateral GaN devices. This 3D integration allows to reduce loop inductance, to ensure more symmetrical design with especially limited Common Mode emission, thanks to a low middle point stray capacitance. This reduction has been achieved by both working on the power layout and including a specific shield between the devices and the heatsink. The performances of this 3D layout have been verified in comparison with a more conventional 2D implementation, using both simulations and measurements.

Autorzy

• Paweł Derkacz link otwiera się w nowej karcie ,
• prof. dr hab. inż. Piotr Chrzan link otwiera się w nowej karcie ,
• dr Pierre-Olivier Jeannin,
• dr hab. inż. Piotr Musznicki link otwiera się w nowej karcie ,
• dr Mickael Petit,
• prof Jean-Luc Schanen